Fast, area-efficient CMOS parity generation

High-performance CMOS parity generator cells are described. Their enhanced speed is derived principally from a combination of exclusive-or and equivalence gate circuits. The circuits realize these logic functions in a single gate level using a combination of fully restoring and pass-transistor gate topology in a semirestoring configuration. The circuits are suitable for the gate forest realization. These parity generator cells neither consume DC power nor require complementary input signals, and are approximately three to five times faster than the conventional dual-level logic implementation. When these circuits are cascaded, the noise margin degradation problems typically associated with nonrestoring logic families are improved. The simplicity of this approach provides significant area savings compared to conventional implementations of various types