Synthesis scheme for low power designs with multiple supply voltages by heuristic algorithms

We present three heuristics synthesis schemes to minimize power consumption with resources operating at multiple voltages under timing and resource constraints. Unlike the conventional methods where only scheduling is considered, all these schemes consider both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve different performance.