DocumentCode
2818097
Title
Applications of Three-Dimensional Topography Simulation in the Design of Interconnect Lines
Author
Sheikholeslami, A. ; Parhami, F. ; Heinzl, R. ; Al-Ani, E. ; Heitzinger, C. ; Badrieh, F. ; Puchner, H. ; Grasser, T. ; Selberherr, S.
Author_Institution
Institute for Microelectronics, TU Vienna, Gußhausstraße 27-29/E360, 1040 Wien, Austria. Phone: +43-1-58801/36034, Fax: +43-1-58801/36099, E-mail: sheikholeslami@iue.tuwien.ac.at
fYear
2005
fDate
01-03 Sept. 2005
Firstpage
187
Lastpage
190
Abstract
We present an analysis of deposition of silicon nitride and silicon dioxide layers into three-dimensional interconnect structures. The investigations have been performed using our general purpose topography simulator ELSA (Enhanced Level Set Applications). We predict void formation and its characteristics, which play an important role for the formation of cracks which are observed during the passivation of layers covering IC chips.
Keywords
Analytical models; Equations; Etching; Geometry; Laboratories; Level set; Microelectronics; Passivation; Silicon; Surface topography;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 2005. SISPAD 2005. International Conference on
Print_ISBN
4-9902762-0-5
Type
conf
DOI
10.1109/SISPAD.2005.201504
Filename
1562056
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