Title :
A fast multiplier design using signed-digit numbers and 3-valued logic
Author :
Chen, I-Shi E. ; Rajashekhara, T.N.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
Abstract :
A multiplier design using 3-valued (ternary) logic and redundant binary signed-digit (RBSD) numbers is presented. The use of 3-valued logic offers the advantage of reduced circuit complexity in terms of both transistor count and interconnections since each ternary bit can support one digit of the RBSD number system. The choice of a RBSD number system enhances the speed of multiplication by allowing carry-free addition of partial products. While the internal multiplication uses RBSD numbers, both the input operands and the output product are assumed to be in the standard two´s complement form. MAGIC and SPICE software tools were used to produce VLSI design layouts and circuit simulation results
Keywords :
circuit layout CAD; digital arithmetic; digital integrated circuits; multiplying circuits; ternary logic; 3-valued logic; MAGIC software; RBSD number system; SPICE software tools; VLSI design layouts; carry-free addition; circuit simulation results; fast multiplier design; interconnections; internal multiplication; output product; reduced circuit complexity; redundant binary signed digit numbers; standard two´s complement form; ternary logic; transistor count; Adders; Arithmetic; Complexity theory; Integrated circuit interconnections; Layout; Logic circuits; Logic design; Multivalued logic; SPICE; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140862
