Design of a Reed-Solomon decoder using a digital signal processor (DSP)

Author

Todoroki, Toshiya ; Miura, Shinji

Author_Institution

NEC Corp., Tokyo, Japan

fYear

1990

fDate

3-6 Sep 1990

Firstpage

443

Lastpage

445

Abstract

The design of a Reed-Solomon (RS) decoder using two digital signal processors (DSP) is discussed. The RS code is a (255, 223) block code of 8-bit symbols which is capable of correcting up to 16 symbol errors. Any primitive polynomial of GF(2⁸) and generator polynomial for a systematic code can be used. The algorithm used for computing the error-locator polynomial is an Euclid´s algorithm. For high-speed decoding, finite field multiplication is carried out by using log and antilog tables in the DSP. A 275 kb/s maximum data transmission rate and 4000 bits for the decoding delay were obtained by using this decoder

Keywords

decoding; digital signal processing chips; error correction codes; 275 kbit/s; 8 bit; DSP; Euclid´s algorithm; Reed-Solomon decoder; antilog tables; block code; data transmission rate; decoding; design; digital signal processor; error-locator polynomial; finite field multiplication; log tables; primitive polynomial; symbol error correction; systematic code; Block codes; Decoding; Digital signal processing; Digital signal processors; Error correction codes; Polynomials; Process design; Reed-Solomon codes; Signal design; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunications Symposium, 1990. ITS '90 Symposium Record., SBT/IEEE International

Conference_Location

Rio de Janeiro

Type

conf

DOI

10.1109/ITS.1990.175644

Filename

175644