Fault diagnosis of switched-capacitor circuits

The authors discuss the application of analogue fault diagnosis strategies to the location of faults in switched-capacitor (SC) integrated circuits. The application of the work is in the prototype testing phase of integrated circuit design and is specifically aimed at locating failures due to parasitic capacitance as well as degradation due to parameter variation and switch failure. The proposed diagnosis strategy comprises three major stages: circuit decomposition; fault location to blocks; and detailed fault analysis within the faulty blocks. Initial work has concentrated upon the final stage of detailed fault analysis via parameter identification. It is recognised that for large systems decomposition it will be necessary to reduce CPU time and to improve the probability of successful diagnosis. This may be carried out by grouping switches, grouping active devices or the introduction of additional test probe points