Title :
Fault testing of analogue macrocells
Author :
Dorey, A.P. ; Silvester, P.J. ; Hibbert, J.B.
Author_Institution :
Dept. of Eng., Lancaster Univ., UK
Abstract :
An increasing number of manufacturers´ are providing analogue integrated circuit functions as macrocells. This development provides parallels with the way in which digital circuits developed and sets new problems of testing particularly when analogue and digital functions are combined in a single chip. The physical mechanisms which give rise to failures in analogue circuits are essentially the same as those that exist in digital circuits. These mechanisms can be divided into those that give rise to hard, open or short circuit, faults or soft, specification, faults. The research reported has concentrated on hard faults in direct coupled analogue circuits. In parallel with the case of digital circuits a fault model is required to represent the faults that are being considered. These have been taken to be either open or short circuits associated with the terminals of the semiconductor devices in the circuit. Such faults may be compiled into a fault dictionary which may be collapsed by identifying groups of faults which result in the same overall measurable circuit behaviour
Keywords :
circuit analysis computing; fault location; integrated circuit testing; linear integrated circuits; analogue integrated circuit functions; analogue macrocells; circuit models; direct coupled analogue circuits; failures; fault dictionary; fault model; hard faults; high level language descriptions; open circuit; piecewise linear models; short circuit; simulation; testing;
Conference_Titel :
VLSI Analogue Design, IEE Colloquium on
Conference_Location :
London