Title :
Very high speed ECL/CML gate arrays with submicron structures
Author :
Mudd, M.S.J. ; Coffey, A.
Author_Institution :
Plessey Semicond. Ltd., Swindon, UK
Abstract :
Describes a very high speed gate array family developed on a 1 micron bipolar process. It is based on a 240 gate prototype which has typical gate delays of 80ps and maximum D-type toggle rate of 3.6GHz
Keywords :
bipolar integrated circuits; emitter-coupled logic; logic arrays; 1 micron; 3.6 GHz; 80 ps; D-type toggle rate; ECL/CML gate arrays; bipolar process; gate delays; submicron structures; very high speed gate array family;
Conference_Titel :
Sub-Micron Silicon Engineering, IEE Colloquium on
Conference_Location :
London
