Fabrication of sub-micron CMOS-SOS devices using direct-write electron beam lithography

Author

Brown, A.G. ; Mortimer, S.H. ; Till, S.J. ; Willis, H. ; Boller, F.D.J. ; Hodge, A.M.

Author_Institution

R. Signals & Radar Establ., Malvern, UK

fYear

1989

fDate

32637

Firstpage

42522

Lastpage

42525

Abstract

In any advanced CMOS process, certain lithographic stages will require the highest resolution, namely the definition of the gates and gate interconnect contact holes and second interconnect layer. Therefore, electron beam lithography has been used at RSRE to produce CMOS-SOS devices with sub-micron gate dimensions. The performance of such devices will be used in future work to identify the processing requirements that will be needed for fully scaled sub-micron SOS transistors

Keywords

CMOS integrated circuits; electron beam lithography; integrated circuit technology; RSRE; contact holes; direct-write electron beam lithography; fully scaled sub-micron SOS transistors; gate interconnect; gates; processing requirements; resolution; second interconnect layer; sub-micron CMOS-SOS devices;

fLanguage

English

Publisher

iet

Conference_Titel

Sub-Micron Silicon Engineering, IEE Colloquium on

Conference_Location

London

Type

conf

Filename

198411

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=281920