DocumentCode :
2819364
Title :
State space reductions for scalable verification of asynchronous designs
Author :
Yao, Haiqiong ; Zheng, Hao ; Myers, Chris J.
Author_Institution :
CSE Dept., Univ. of South Florida, Tampa, FL, USA
fYear :
2010
fDate :
10-12 June 2010
Firstpage :
17
Lastpage :
24
Abstract :
This paper presents several state space reductions for verifying non-trivial asynchronous designs with a compositional minimization approach. These reductions result in a reduced model that contains the exact set of observably equivalent behavior. Therefore no false counter-examples are produced at the end of verification. The experimental results show good scale-up of compositional minimization using these reductions on a number of asynchronous designs.
Keywords :
formal verification; asynchronous designs; compositional minimization; scalable verification; state space reductions; Algorithm design and analysis; Concrete; Design methodology; Explosions; Learning automata; State-space methods; System recovery;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE International
Conference_Location :
Anaheim, FL
ISSN :
1552-6674
Print_ISBN :
978-1-4244-7805-7
Type :
conf
DOI :
10.1109/HLDVT.2010.5496666
Filename :
5496666
Link To Document :
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