• DocumentCode
    2819495
  • Title

    Minimizing ECO routing for FIB

  • Author

    Wu, Yun-Ru ; Kao, Shu-Yi ; Hwang, Shih-Arn

  • Author_Institution
    Realtek Semicond. Corp., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    26-29 April 2010
  • Firstpage
    351
  • Lastpage
    354
  • Abstract
    Engineering Change Order (ECO) routing is often requested in later design stages even after chip manufacturing. We propose an ECO routing method that can reuse most existing routing pattern to implement the modifications. In current industrial design methodologies, designers often take advantage of FIB (Focused Ion Beam) process when they need functional changes and/or bug fixings as soon as possible after chip manufacturing. Therefore, we apply our method to do circuit modifications in the FIB system, which is commonly used to slightly modify an existing circuit by cutting unwanted electrical connections and depositing conductive material to make a connection. However the exact coordinates on the circuit are necessary before using the FIB system, because the FIB system cuts and re-wires connections according to the given coordinates, and those FIB locations must be conformed to pre-specified conditions and follow certain guidelines. As design complexity increases rapidly, ECO routing in designs with high metal density becomes more and more difficult, and the successful rate is becoming lower. The ECO routing method we proposed can effectively apply to the FIB system for finding the layout locations and using the minimum FIB processes, which leads to successful FIB results.
  • Keywords
    focused ion beam technology; integrated circuit design; network routing; ECO routing; FIB; engineering change order routing; focused ion beam; Circuits; Conducting materials; Costs; Design methodology; Guidelines; Ion beams; Routing; Scanning electron microscopy; Semiconductor device manufacture; Semiconductor materials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
  • Conference_Location
    Hsin Chu
  • Print_ISBN
    978-1-4244-5269-9
  • Electronic_ISBN
    978-1-4244-5271-2
  • Type

    conf

  • DOI
    10.1109/VDAT.2010.5496675
  • Filename
    5496675