Verifying thermal/thermo-mechanical behavior of a 3D stack - challenges and solutions

Author

Marchal, Paul ; Van der Plas, Geert ; Limaye, Paresh ; Mercha, Abdelkarim ; Cherman, Vladimir ; O´Prins, Herman ; Labie, Riet ; Vandevelde, Bart ; Travaly, Youssef ; Beyne, Eric

Author_Institution

IMEC, Leuven, Belgium

fYear

2010

fDate

26-29 April 2010

Firstpage

15

Lastpage

16

Abstract

The paper describes the design challenges for a low-cost 3D Cu-TSV technology. Based on experimental characterization, we´ll indicate the importance of thermal and thermo-mechanical challenges. To avoid related yield loss and/or reliability issues, thermo-mechanical and thermal hotspots should be re-solved in early phases of the design flow. We will present a possible design flow hereto based on the concept of “smart mechanical samples”.

Keywords

integrated circuit design; integrated circuit metallisation; integrated circuit packaging; thermal management (packaging); three-dimensional integrated circuits; 3D Cu-TSV technology; Cu; design flow; smart mechanical sample; thermal behavior; thermo-mechanical behavior; through silicon via; Costs; Packaging; Power dissipation; Random access memory; Temperature measurement; Thermal management; Thermal stresses; Thermomechanical processes; Threshold voltage; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on

Conference_Location

Hsin Chu

Print_ISBN

978-1-4244-5269-9

Electronic_ISBN

978-1-4244-5271-2

Type

conf

DOI

10.1109/VDAT.2010.5496679

Filename

5496679