DocumentCode
2819594
Title
Via mid through silicon vias - the manufacturability outlook
Author
Arkalgud, Sitaram
Author_Institution
SEMATECH, Albany, NY, USA
fYear
2010
fDate
26-29 April 2010
Firstpage
17
Lastpage
18
Abstract
The potential for via-mid through-silicon vias (TSVs) can be considerable, since their use allows not only a reduction in interconnect length from several mm to several microns, but also a tremendous increase in bandwidth between the stacked chips. The net result is less power consumption, higher performance, increased device density within a given chip footprint, and greater potential to integrate diverse technologies at an overall lower cost. This presentation will cover the manufacturability outlook for via-mid TSVs including equipment, process, and metrology maturity.
Keywords
design for manufacture; integrated circuit interconnections; silicon; chip footprint; device density; interconnect length; manufacturability outlook; power consumption; stacked chips; via mid through silicon vias; Acoustic signal detection; Costs; Infrared detectors; Manufacturing; Metrology; Scanning electron microscopy; Silicon; Through-silicon vias; Transmission electron microscopy; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location
Hsin Chu
Print_ISBN
978-1-4244-5269-9
Electronic_ISBN
978-1-4244-5271-2
Type
conf
DOI
10.1109/VDAT.2010.5496680
Filename
5496680
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