Low-Power FinFET design schemes for NOR address decoders

This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes´ performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs´ back gates are reverse-biased for lower-power operation, was used as the base scheme for comparisons. The Shorted-Gate (SG) High Precharge Swing scheme has a better performance tradeoff than the other presented schemes, including the LP scheme. While dynamic power is 10.9% to 11.9% more than the LP scheme, the SG-High Precharge Swing scheme is 48.1% to 59.9% faster and dissipates 93.0% to 99.7% less leakage power than the LP scheme. In addition, the SG-High Precharge Swing scheme requires less supporting hardware as it needs one less voltage level and one less voltage conversion buffer than the LP scheme.