A 65nm CMOS dual-band RF receiver front-end for DVB-H

Author

Shih, Yi-Shing ; Kuo, Ming-Ching

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2010

fDate

26-29 April 2010

Firstpage

83

Lastpage

86

Abstract

A dual-band RF receiver front-end for DVB-H is presented in this paper. It includes two sets of single-ended input LNAs, respectively followed by a double-balanced current-driven passive mixer with a low impedance load. The receiver front-end is implemented in a 1P6M 65 nm CMOS process and occupies a total chip area of 2.17 mm². It exhibits a conversion gain of 36.5 dB, an IIP3 of -13.1 dBm, an IIP2 of 37 dBm, and a NF of 3.9-4.2 dB in the UHF band, while exhibiting a conversion gain of 37 dB, an IIP3 of -12 dBm, an IIP2 of better than 33 dBm, and a NF of 5.5 dB in the L-band. The total chip draws 32-34mA from a 1.2 V supply voltage.

Keywords

CMOS integrated circuits; UHF amplifiers; UHF integrated circuits; UHF mixers; digital video broadcasting; low noise amplifiers; radio receivers; CMOS dual band RF receiver; UHF band; current 32 mA to 34 mA; double balanced current driven passive mixer; front end for DVB-H; low impedance load; single ended input LNA; size 65 nm; voltage 1.2 V; Broadband amplifiers; CMOS technology; Character generation; Digital video broadcasting; Dual band; Impedance matching; L-band; Noise measurement; Radio frequency; Tuners; CMOS RF; DVB-H; balun; noise-canceling; wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on

Conference_Location

Hsin Chu

Print_ISBN

978-1-4244-5269-9

Electronic_ISBN

978-1-4244-5271-2

Type

conf

DOI

10.1109/VDAT.2010.5496697

Filename

5496697