Title :
Yield-enhancement techniques for 3D random access memories
Author :
Chou, Che-Wei ; Huang, Yu-Jen ; Li, Jin-Fu
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Abstract :
Three-dimensional (3D) integration technology using through silicon via (TSV) is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for using the 3D integration technology. Introducing redundancies into a large-capacity RAM in design phase is essential for yield improvement. In this paper, we present yield-enhancement techniques for 3D RAMs. In addition to typical redundancy schemes are used to improve the yield of 3D RAMs, an inter-die redundancy scheme is proposed. Also, a stacking flow is proposed to further improve the final yield of 3D RAMs with the proposed inter-die redundancy scheme.
Keywords :
integrated circuit design; integrated circuit yield; integrated memory circuits; three-dimensional integrated circuits; 3D integration technology; 3D random access memories; RAM; integrated circuit designs; inter-die redundancy scheme; three-dimensional integration technology; through silicon via; yield-enhancement techniques; Integrated circuit reliability; Integrated circuit technology; Integrated circuit yield; Random access memory; Read-write memory; Redundancy; Silicon; Stacking; Testing; Through-silicon vias;
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
DOI :
10.1109/VDAT.2010.5496702
