DocumentCode
2819983
Title
ATE assisted test response compaction
Author
Howard, J.M. ; Reddy, S.M. ; Pomeranz, I.
Author_Institution
Dept. of ECE, Univ. of Iowa, Iowa City, IA, USA
fYear
2010
fDate
26-29 April 2010
Firstpage
112
Lastpage
115
Abstract
A new method for achieving test response compaction is proposed. The method involves testers to achieve additional compaction, without compromising fault coverage, beyond what may be already achieved using on-chip response compactors. The method does not add additional logic or modify the circuit under test or require additional tests and thus can be used with any design including legacy designs. Simple heuristic procedures are used to achieve additional compaction. Experimental results on larger ISCAS-89 circuits show the effectiveness of the method.
Keywords
automatic test equipment; logic testing; ATE; test response compaction; Automatic testing; Chromium; Circuit faults; Circuit testing; Compaction; Integrated circuit testing; Logic design; Logic testing; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location
Hsin Chu
Print_ISBN
978-1-4244-5269-9
Electronic_ISBN
978-1-4244-5271-2
Type
conf
DOI
10.1109/VDAT.2010.5496704
Filename
5496704
Link To Document