Title :
CMOS high-resolution all-digital phase-locked loop
Author :
Mokhtari, E. ; Savvan, M.
Author_Institution :
Dept. of Electr. Eng., PolySTIM Neurotechnology Lab., Montreal, Que.
Abstract :
The core of an all-digital phase locked-loop (ADPLL) is composed of a high resolution digital controlled oscillator (DCO) circuit operating in a wide frequency range, a phase-frequency detector (PFD) and an up/down binary counter. The ADPLL can be reused in many system-on-chip (SoC) applications by a proper setting of the DCO and the PFD. Extensive simulation were carried on using models of a standard 0.18mum CMOS technology, with a power supply of 1.8 volts. The simulation results show that the ADPLL can operate from 26MHz to 588MHz
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; digital phase locked loops; system-on-chip; 0.18 micron; 1.8 V; 26 to 588 MHz; CMOS all-digital phase-locked loop; binary counter; digital controlled oscillator; phase-frequency detector; system-on-chip application; CMOS technology; Circuit simulation; Counting circuits; Digital control; Digital-controlled oscillators; Phase detection; Phase frequency detector; Phase locked loops; Semiconductor device modeling; System-on-a-chip;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Conference_Location :
Cairo
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562258
