Abstract :
In this paper, we design different type of SRAM cells. This paper compares the performance of five SRAM cell topologies, which include the conventional 6T, 7T, 8T, 9T and the 10T SRAM cell implementations. In particular, the leakage currents, leakage power and read behaviour of each SRAM cells are examined. In 10T SRAM cell implementation results, reduced leakage power and leakage current by 36% and 64% respectively, the read stability is increased by 13% over conventional 6T, 7T, 8T and 9T SRAM cells. As a result, the 10T SRAM always consumes lowest leakage power and leakage current; improve read stability as compared to the 6T, 7T, 8T and 9T SRAM cells. The aim of this paper is to reduce the leakage power, leakage current and improve the read behaviour of the different SRAM cell structures using cadence tool at 45nm technology while keeping the read and write access time and the power as low as possible.
Keywords :
SRAM chips; integrated circuit design; network topology; 6T SRAM cell implementation; 7T SRAM cell implementation; 8T SRAM cell implementation; 9T SRAM cell implementation; SRAM cell topology design; cadence tool; leakage current reduction; leakage power reduction; read access time; read behaviour; read stability; size 45 nm; write access time; Circuit stability; Leakage currents; Logic gates; MOSFET; SRAM cells; Leakage Current; Leakage Power; Low Power; Read Stability; SRAM Cell;
