DocumentCode :
2820205
Title :
Methods for boundary scan access of built-in self-test for field programmable gate arrays
Author :
Hamilton, Carter ; Wijesuriya, Sajitha ; Gibson, Gretchen ; Stroud, Charles
Author_Institution :
Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
fYear :
1999
fDate :
1999
Firstpage :
210
Lastpage :
216
Abstract :
In this paper we present four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard boundary scan interface along with the advantages and disadvantages of each approach. Each method is evaluated with consideration to test time, logic overhead, diagnostics resolution, usability in FPGAs, and architectural features which would be required to implement the approach. These methods can be used in a variety of FPGA architectures for all levels of testing
Keywords :
IEEE standards; automatic testing; boundary scan testing; built-in self test; field programmable gate arrays; integrated circuit testing; logic testing; IEEE 1149.1 standard boundary scan interface; architectural features; boundary scan access; built-in self-test; diagnostics resolution; field programmable gate arrays; logic overhead; test time; Built-in self-test; Circuit testing; Control systems; Field programmable gate arrays; Logic circuits; Logic testing; Pins; Reconfigurable logic; System testing; Usability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Southeastcon '99. Proceedings. IEEE
Conference_Location :
Lexington, KY
Print_ISBN :
0-7803-5237-8
Type :
conf
DOI :
10.1109/SECON.1999.766126
Filename :
766126
Link To Document :
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