DocumentCode :
2820207
Title :
High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate
Author :
Kazior, T.E. ; Laroche, J.R. ; Urteaga, M. ; Bergman, J. ; Choe, M.J. ; Lee, K.J. ; Seong, T. ; Seo, M. ; Yen, A. ; Lubyshev, D. ; Fastenau, J.M. ; Liu, W.K. ; Smith, D. ; Clark, D. ; Thompson, R. ; Bulsara, M.T. ; Fitzgerald, E.A. ; Drazek, C. ; Guiot, E
Author_Institution :
Raytheon Integrate Defense Syst., Andover, MA, USA
fYear :
2010
fDate :
3-6 Oct. 2010
Firstpage :
1
Lastpage :
4
Abstract :
We present recent results on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon template wafer or SOLES (Silicon On Lattice Engineered Substrate). InP HBTs whose performance are comparable to HBTs on the native InP substrates have been repeatedly achieved. 100% heterogeneous interconnect yield has been achieved on daisy chain test structures with CMOS-InP HBT spacing (interconnect length) as small as 2.5um. In DARPA COSMOS Phase 1 we designed and fabricated a differential amplifier that met the program Go/NoGo metrics with first pass design success. As the COSMOS Phase 2 demonstration vehicle we designed and fabricated a low power dissipation, high resolution, 500MHz bandwidth digital-to-analog converter (DAC).
Keywords :
CMOS integrated circuits; III-V semiconductors; differential amplifiers; digital-analogue conversion; heterojunction bipolar transistors; indium compounds; integrated circuit interconnections; mixed analogue-digital integrated circuits; monolithic integrated circuits; silicon; CMOS; COSMOS Phase 2 demonstration vehicle; DAC; DARPA COSMOS Phase 1; HBT; InP; SOLES; bandwidth digital-to-analog converter; daisy chain test structures; differential amplifier; direct heterogeneous integration; direct monolithic heterogeneous integration; heterogeneous interconnect yield; high performance mixed signal circuits; interconnect length; low power dissipation; silicon on lattice engineered substrate; silicon substrate; silicon template wafer; CMOS integrated circuits; Differential amplifiers; Heterojunction bipolar transistors; Indium phosphide; Integrated circuit interconnections; Silicon; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010 IEEE
Conference_Location :
Monterey, CA
ISSN :
1550-8781
Print_ISBN :
978-1-4244-7437-0
Electronic_ISBN :
1550-8781
Type :
conf
DOI :
10.1109/CSICS.2010.5619670
Filename :
5619670
Link To Document :
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