Yield modeling for majority voting based defect-tolerant VLSI circuits

Author

Stroud, Charles E.

Author_Institution

Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA

fYear

1999

fDate

1999

Firstpage

229

Lastpage

236

Abstract

A yield model is developed for generalized N-tuple modular redundancy (NMR) based defect-tolerant designs. The yield model is both mathematical and simulation based where the simulation portion uses a random multiple fault injection simulation procedure while the mathematical portion accounts for defect clustering in the fabrication process. Analysis of the yield model and comparison with empirical data from actual wafer fabrications shows the model to be accurate. The NMR based approach to defect-tolerance in VLSI designs is most practical for application in gate arrays and pad-limited full and semi-custom VLSI

Keywords

VLSI; application specific integrated circuits; digital integrated circuits; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; logic arrays; probability; redundancy; defect clustering; fabrication process; gate arrays; generalized N-tuple modular redundancy; majority voting based defect-tolerant VLSI circuits; pad-limited full custom VLSI; pad-limited semicustom VLSI; random multiple fault injection simulation procedure; yield model; Circuit faults; Circuit simulation; Fabrication; Integrated circuit yield; Mathematical model; Nuclear magnetic resonance; Redundancy; Semiconductor device modeling; Very large scale integration; Voting;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '99. Proceedings. IEEE

Conference_Location

Lexington, KY

Print_ISBN

0-7803-5237-8

Type

conf

DOI

10.1109/SECON.1999.766130

Filename

766130