Title :
Reachability analysis of sequential circuits
Author :
Tsai, Jung-Tai ; Wang, Chun-Yao ; Chang, Kuang-Jung
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Reachability analysis is a fundamental technique in the synthesis, verification of VLSI circuits. This paper presents a novel semi-formal approach which combines the advantages of simulation and formal methods to traverse the state space of the FSMs. We conduct the experiments on a set of ISCAS´89 benchmarks. Compared with a previous work which relies on biased random technique, our approach reaches more states with less CPU time.
Keywords :
VLSI; finite state machines; integrated circuit design; integrated logic circuits; logic design; sequential circuits; CPU time; FSM; ISCAS´89 benchmarks; VLSI circuit synthesis; VLSI circuit verification; formal method; reachability analysis; semiformal approach; sequential circuits; simulation method; state space; Binary decision diagrams; Boolean functions; Circuit simulation; Computer bugs; Data structures; Flip-flops; Reachability analysis; Sequential circuits; State-space methods; Very large scale integration;
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
DOI :
10.1109/VDAT.2010.5496720
