DocumentCode :
2820329
Title :
LNA Design Based on an Extracted Single Gate Finger Model
Author :
Mahon, Simon J. ; Dadello, Anna ; Vun, Peter ; Tarazi, Jabra ; Young, Alan C. ; Heimlich, Michael C. ; Harvey, James T. ; Parker, Anthony E.
Author_Institution :
M/A-COM Technol. Solutions, North Sydney, NSW, Australia
fYear :
2010
fDate :
3-6 Oct. 2010
Firstpage :
1
Lastpage :
4
Abstract :
A GaAs low-noise amplifier (LNA) is designed with first-time success using a technique for HEMT modelling which divides the device into intrinsic gate fingers embedded in an analysable metal structure. The gate finger is characterised by de-embedding metallisation from a standard test structure. The device is then re-built, with any geometry or layout that the foundry allows, and modelled by electromagnetic (EM) analysis. This allows techniques such as asymmetric inductive source feedback in an LNA to be modelled without prior fabrication of custom test structures. The 7-13 GHz, self-biased LNA has state-of-the-art noise figure (NF) of 1.25 dB at mid-band, gain of 20.5 ± 0.1 dB with 10 dB input and output matches, 10 dBm P1dB, 14 dBm Psat and 22 dBm OIP3. Excellent agreement is achieved with simulation. In a 3 × 3 QFN package the measured NF is 1.36 dB and the gain is 20 dB. The first-time design success achieved here validates the modelling and parameter extraction technique.
Keywords :
III-V semiconductors; gallium arsenide; high electron mobility transistors; low noise amplifiers; microwave amplifiers; semiconductor device metallisation; GaAs; HEMT modelling; LNA design; asymmetric inductive source feedback; deembedding metallisation; electromagnetic analysis; frequency 7 GHz to 13 GHz; gain 20 dB; geometry; low-noise amplifier; metal structure; noise figure 1.25 dB; noise figure 1.36 dB; parameter extraction; self-biased LNA; single gate finger model; Fingers; HEMTs; Integrated circuit modeling; Layout; Logic gates; Microstrip; Noise measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010 IEEE
Conference_Location :
Monterey, CA
ISSN :
1550-8781
Print_ISBN :
978-1-4244-7437-0
Electronic_ISBN :
1550-8781
Type :
conf
DOI :
10.1109/CSICS.2010.5619678
Filename :
5619678
Link To Document :
بازگشت