FPGA implementation of data hididng in grayscale imagesusing neighbour mean interpolation

Author

Sakthivel, S.M. ; Sankar, A. Ravi

Author_Institution

SENSE, VIT Univ., Chennai, India

fYear

2015

fDate

26-27 Feb. 2015

Firstpage

1124

Lastpage

1127

Abstract

Data hiding in one of the easiest technique to authenticate and resolve the copyright issues of multimedia data. This paper proposes a new VLSI architecture for data hiding in grayscale images using neighbour mean image interpolation technique, as this mechanism will have a minimum computation complexity. In this VLSI based data hiding process the secret digital signature is hidden in the host image and analyzed with the PSNR value and Payload capacity.

Keywords

VLSI; data encapsulation; digital signatures; field programmable gate arrays; image processing; interpolation; FPGA implementation; PSNR value; VLSI based data hiding process; computation complexity; grayscale images; neighbour mean image interpolation technique; payload capacity; secret digital signature; Data mining; Image resolution; Interpolation; Multimedia communication; Real-time systems; Very large scale integration; Watermarking; Gray Scale Image; Neighbor mean interpolation; Real Time Data Hiding/Watermarking; Reversible data hiding; Spatial domain embedding;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics and Communication Systems (ICECS), 2015 2nd International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-7224-1

Type

conf

DOI

10.1109/ECS.2015.7124758

Filename

7124758