Inter and intra kernel reuse analysis driven pipelining on Chip-Multiprocessors

As the demand for low power multimedia systems continues to grow, so will the need for low cost and efficient solutions. Driven by such need, as well as improvements IC design technology, Chip-Multiprocessors (CMPs) have emerged as a potential solution. CMPs offer flexibility, low cost, low power and the ability to handle highly parallel workloads. As CMPs scale, it is up to the designer to take full advantage of their computational resources and manage their constrained memory resources efficiently. In this paper we propose a methodology that enables designers to fully exploit the target platform´s computational resources without sacrificing power consumption by maximizing the application´s reuse. Our approach uses code transformations to split the application´s tasks into smaller units of computations or subtasks called kernels. Each kernel is analyzed for inter and intra reuse opportunities in order to minimize unnecessary data transfers between kernels. Our approach also couples both scheduling/pipelining of tasks with their memory allocations. This allows us to obtain memory aware pipelined schedules that increases throughput and reduces power consumption. Our methodology has shown up to 15% performance improvements as well as 33% power reduction when compared to state of the art techniques.