• DocumentCode
    2820378
  • Title

    A 4 by 28.3 Gb/s SFI-S SerDes in 130 nm SiGe

  • Author

    Krawczyk, Thomas ; Cooper, Todd ; Steidl, Samuel ; Curran, Peter ; Yamagata, Masashi ; Shang, Song ; Liu, Tony ; Pulver, James ; Duong, Cliff ; Wang, Zuoding ; Walworth, Darren ; Hornbuckle, Craig ; Rowe, David

  • fYear
    2010
  • fDate
    3-6 Oct. 2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A 4 by 28.3 to 10 by 11.32 Gb/s SFI-S compliant two chip SerDes for 100 Gb/s applications was fabricated using IBM´s SiGe 130 nm 8HP process (210 GHz fT). The Multiplexer receives 10 channels, plus the SFI-S deskew channel at 11.32 Gb/s, and outputs four lanes at 28.3 Gb/s, with a maximum output of 1.2 Vpp differential. The Demultiplexer receives four channels at 28.3 Gb/s, recovers clock and data with a sensitivity of 40 mV, and outputs 10 channels, plus the SFI-S deskew channel at 11.32 Gb/s.
  • Keywords
    demultiplexing; multiplexing; optical switches; IBM SiGe 130 nm 8HP process; SFI-S deskew channel; bit rate 28.3 Gbit/s; compliant two chip SerDes; demultiplexer; size 130 nm; CMOS integrated circuits; Clocks; Jitter; Multiplexing; Optical device fabrication; Tuning; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010 IEEE
  • Conference_Location
    Monterey, CA
  • ISSN
    1550-8781
  • Print_ISBN
    978-1-4244-7437-0
  • Electronic_ISBN
    1550-8781
  • Type

    conf

  • DOI
    10.1109/CSICS.2010.5619681
  • Filename
    5619681