A 204.8GHz Static Divide-by-8 Frequency Divider in 250nm InP HBT

Author

Griffith, Zach ; Urteaga, Miguel ; Pierson, Richard ; Rowell, Petra ; Rodwell, Mark ; Brar, Bobby

Author_Institution

Teledyne Sci. Co., Thousand Oaks, CA, USA

fYear

2010

fDate

3-6 Oct. 2010

Firstpage

1

Lastpage

4

Abstract

We present a static divide-by-8 frequency divider with a record maximum clock frequency of 204.8GHz, designed and fabricated using 250nm InP HBTs (400GHz f_τ, 650GHz f_max) with a 4-metal layer, inverted thin-film microstrip wiring environment. The divider is fully static down to 4.0GHz operation. The total power dissipation is 1.82W, of which 592mW is consumed by the input-stage divider. The divider latches are formed using emitter-coupled-logic (ECL), and inductive peaking is used in series with the load resistance R_L to minimize gate delays for highest possible divider clock rates. The circuit contains 108 HBTs and its size is 0.68 x 0.45-mm².

Keywords

III-V semiconductors; emitter-coupled logic; frequency dividers; heterojunction bipolar transistors; indium compounds; HBT; InP; emitter-coupled logic; frequency 204.8 GHz; frequency 4.0 GHz; frequency 400 GHz; frequency 650 GHz; inductive peaking; inverted thin-film microstrip wiring environment; load resistance; power 1.82 W; power 592 mW; size 250 nm; static divide-by-8 frequency divider; Clocks; Frequency conversion; Frequency measurement; Heterojunction bipolar transistors; Indium phosphide; Integrated circuit interconnections;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010 IEEE

Conference_Location

Monterey, CA

ISSN

1550-8781

Print_ISBN

978-1-4244-7437-0

Electronic_ISBN

1550-8781

Type

conf

DOI

10.1109/CSICS.2010.5619684

Filename

5619684