DocumentCode :
2820496
Title :
A Verilog-A Large-Signal GaN HEMT Model for High Power Amplifier Design
Author :
Kharabi, F. ; McMacken, J.R.F. ; Gering, J.M.
Author_Institution :
Corp. Eng., III-V Modeling, RF Micro Devices, Inc. (RFMD), Greensboro, NC, USA
fYear :
2010
fDate :
3-6 Oct. 2010
Firstpage :
1
Lastpage :
4
Abstract :
This paper describes the high-power non-linear modeling of a GaN HEMT device using a Verilog-A-implemented and modified version of the EEHEMT model commonly found in commercial simulators. As discussed in, peculiarities of GaN device physics exposed flaws in the standard EEHEMT model such as the inability to describe trap-related phenomena such as knee walk-out, multiple voltage dependencies of conduction currents, anomalies in the saturation current/conductance, and nonlinear behavior of source resistance. Improvements were made to the standard model to accommodate GaN-specific characteristics of the knee and saturation regions of the device IV plane as well as a functional dependence of Rs on RF operating current. Additionally, temperature dependencies were implemented in the Verilog-A version using a thermal sub-circuit to account for self-heating in real-time and ambient temperature effects. Extensive pulsed and CW load-pull measurements were done at multiple source/load states and power levels and at several frequencies. Output power, gain, efficiency and load-pull contour simulations vs. measurements are presented. The improved model is shown to accurately predict actual device and scaled high-power amplifier behavior and has proven to be a useful tool in very high power product design.
Keywords :
high electron mobility transistors; power amplifiers; GaN; HEMT device; Verilog-A; commercial simulator; high power amplifier behavior; high power amplifier design; high power nonlinear modeling; high power product design; load-pull contour simulation; standard EEHEMT model; temperature dependency; Gallium nitride; HEMTs; Load modeling; Power amplifiers; Power generation; Resistance; Temperature measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010 IEEE
Conference_Location :
Monterey, CA
ISSN :
1550-8781
Print_ISBN :
978-1-4244-7437-0
Electronic_ISBN :
1550-8781
Type :
conf
DOI :
10.1109/CSICS.2010.5619689
Filename :
5619689
Link To Document :
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