A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression

Author

Hung, Chao-Ching ; Chen, I-Fong ; Liu, Shen-Iuan

fYear

2010

fDate

26-29 April 2010

Firstpage

237

Lastpage

240

Abstract

A fast-locked all-digital phase-locked loop (PLL) with supply noise suppression is presented. The analysis and design of this all-digital PLL is presented. While the supply noise exits, the loop bandwidth of this all-digital PLL is dynamically adjusted to suppress the jitter. This all-digital PLL is fabricated in a 0.18 um CMOS process. It achieves the locked time of 22.5 us and 78 us with and without the fast-locked circuit, respectively. The measured peak-to-peak jitter and rms jitter are 38.9 ps and 5.9ps, respectively, at 1.25 GHz.

Keywords

CMOS digital integrated circuits; UHF integrated circuits; digital phase locked loops; interference suppression; jitter; CMOS process; PLL; all-digital phase-locked loop; fast-locked circuit; frequency 1.25 GHz; jitter suppression; size 0.18 mum; supply noise suppression; time 22.5 mus; time 78 mus; Bandwidth; Circuit noise; Clocks; Detectors; Digital-controlled oscillators; Frequency; Jitter; Phase detection; Phase locked loops; Phase noise; all-digital; fast-locked; phase-locked loop; supply noise suppression;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on

Conference_Location

Hsin Chu

Print_ISBN

978-1-4244-5269-9

Electronic_ISBN

978-1-4244-5271-2

Type

conf

DOI

10.1109/VDAT.2010.5496733

Filename

5496733