Optimum leakage dynamic array design

In recent microprocessor designs Register File (RF) and Read Only Memory (ROM) arrays comprise over 50% of the total core area. These arrays account for a significant portion of the total leakage power. We propose two novel design techniques: Tri-state Domino Circuit (TDC) and Selective Pre-Charge (SPC). We combine these techniques to maximize leakage savings without affecting downstream logic by using a new noise robust state preserving Set Dominant Latch (SDL). Our simulation results, in 32nm CMOS technology, demonstrate that we are able to reduce the read path leakage power for a 256 entry 1 rlw RF by 81%.