DocumentCode :
2820705
Title :
Scheduling critical channels in conservative parallel discrete event simulation
Author :
Xiao, Z. ; Unger, B. ; Simmonds, R. ; Cleary, J.
Author_Institution :
Dept. of Comput. Sci., Calgary Univ., Alta., Canada
fYear :
1999
fDate :
1999
Firstpage :
20
Lastpage :
28
Abstract :
This paper introduces the Critical Channel Traversing (CCT) algorithm, a new scheduling algorithm for both sequential and parallel discrete event simulation. CCT is a general conservative algorithm that is aimed at the simulation of low-granularity network models on shared-memory multiprocessor computers. An implementation of the CCT algorithm within a kernel called TasKit has demonstrated excellent performance for large ATM network simulations when compared to previous sequential, optimistic and conservative kernels. TasKit has achieved two to three times speedup on a single processor with respect to a splay tree central-event-list based sequential kernel. On a 16 processor (R8000) Silicon Graphics PowerChallenge, TasKit has achieved an event-rate of 1.2 million events per second and a speedup of 26 relative to the sequential kernel for a large ATM network model. Performance is achieved through a multi-level scheduling scheme that supports the scheduling of large grains of computation even with low-granularity events. Performance is also enhanced by supporting good cache behavior and automatic load balancing. The paper describes the algorithm and its motivation, proves its correctness and briefly presents performance results for TasKit
Keywords :
discrete event simulation; parallel processing; resource allocation; scheduling; shared memory systems; software performance evaluation; telecommunication computing; ATM network simulations; Critical Channel Traversing algorithm; Silicon Graphics PowerChallenge; TasKit; automatic load balancing; cache; central-event-list; conservative algorithm; conservative parallel discrete event simulation; critical channel scheduling; low-granularity network models; multi-level scheduling; performance; shared-memory multiprocessor computers; splay tree; Computational modeling; Computer networks; Computer simulation; Discrete event simulation; Graphics; Kernel; Processor scheduling; Scheduling algorithm; Silicon; Tree graphs;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Simulation, 1999. Proceedings. Thirteenth Workshop on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7695-0155-9
Type :
conf
DOI :
10.1109/PADS.1999.766157
Filename :
766157
Link To Document :
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