Title :
A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application
Author :
Xu, Hongtao ; Palaskas, Yorgos ; Ravi, Ashoke ; Soumyanath, Krishnamurthy
Author_Institution :
Radio Integration Res., Intel Labs., Hillsboro, OR, USA
Abstract :
An outphasing power amplifier (PA) is designed and implemented in a 32nm digital CMOS process. The PA uses a transformer power combining configuration with reduced losses at backoff power. In the range of 2.2-2.5GHz, this PA gives 25dBm peak CW power with 40% total efficiency (includes all drivers). The class-D PA takes advantage of 32nm switching speed to achieve good linearity performance. The PA delivers 18dBm average power with 18% total efficiency while meeting 64-QAM WLAN requirements, with no need for linearization.
Keywords :
CMOS digital integrated circuits; UHF power amplifiers; wireless LAN; 64-QAM WLAN requirements; WLAN application; class-D PA; digital CMOS process; frequency 2.2 GHz to 2.5 GHz; highly linear 25dBm outphasing power amplifier; size 32 nm; switching speed; transformer power; CMOS integrated circuits; Driver circuits; Power amplifiers; Radio frequency; System-on-a-chip; Transistors; Wireless LAN;
Conference_Titel :
ESSCIRC, 2010 Proceedings of the
Conference_Location :
Seville
Print_ISBN :
978-1-4244-6662-7
DOI :
10.1109/ESSCIRC.2010.5619705
