Title :
A high performance binary TO BCD converter for decimal multiplication
Author :
Bhattacharya, Jairaj ; Gupta, Aman ; Singh, Anshul
Author_Institution :
Centre for VLSI & Embedded Syst. Technol. (CVEST), Int. Inst. of Inf. Technol. (IIIT), Hyderabad, India
Abstract :
Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. Binary to BCD conversion forms the basic building block of decimal digit multipliers. This paper presents novel high speed low power architecture for fixed bit binary to BCD conversion which is at least 28% better in terms of power-delay product than the existing designs.
Keywords :
arithmetic codes; binary codes; binary sequences; binary coded decimal; binary to BCD converter; decimal arithmetic; decimal data processing; decimal digit multipliers; decimal multiplication; high speed low power architecture; power-delay product; Business; Data processing; Delay; Embedded system; Energy consumption; Floating-point arithmetic; Hardware; Information technology; Internet; Very large scale integration;
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
DOI :
10.1109/VDAT.2010.5496752
