A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS

This paper presents a low-power Class-D stage featuring a new harmonic reduction technique, which cancels the 3^rd harmonic and reduces the 5^th harmonic. The technique creates a voltage level of V_DD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. From a single Class-D stage operating at 900MHz, the measured output power is +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% for a 1.2V supply, while 2^nd to 4^th harmonics are measured to be -37dBc without any filtering. Connecting two Class-D stages to a PCB-mounted transformer in an outphasing configuration, the overall amplifier is linear enough to amplify EDGE 8-PSK and WCDMA modulated signals at 900MHz without pre-distortion of the input signals or any other linearization technique.