Quadruple filtering schedule for H.264/AVC deblocking filter

This paper presents a quadruple filtering schedule for high-throughput rate H.264 deblocking filter. This innovation is achieved by considering both luminance and chrominance data at the same time in arranging the filtering schedule. Furthermore, this paper discloses an embodiment for the proposed quadruple filtering schedule. The disclosed embodiment adopts interleave memory organization to eliminate all the data conflicts occurred during the deblocking filtering. Hence, the resulting deblocking filter can process one edge filtering per cycle. After being implemented by using a 0.18-μm CMOS technology, this work can achieve the real-time performance requirement of 6K (6000 × 4000@30fps) application when operated at 135 MHz frequency at the cost of 41.6k gates along with 640 bytes single-port SRAM. Compared with previous works, the proposed design not only achieves higher real-time performance requirements but also provides a good trade-off between enhancing the performance and reducing the memory access.