Title :
Using the charge recycling technique for low power PLA design
Author :
Xiao, Chiuan-Tai ; Wei, Kai-Cheng
Author_Institution :
Grad. Inst. of Integrated Circuit Design, Nat. Changhua Univ. of Educ., Changhua, Taiwan
Abstract :
This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.
Keywords :
CMOS logic circuits; logic design; low-power electronics; programmable logic arrays; CMOS; charge recycling circuit; charge recycling technique; charge-recycling techniques; low power PLA design; power consumption; power delay product; product lines swing voltage; programmable logic array; size 0.35 mum; Capacitors; Cities and towns; Computer science education; Delay; Digital circuits; Educational programs; Energy consumption; Programmable logic arrays; Recycling; Voltage;
Conference_Titel :
VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on
Conference_Location :
Hsin Chu
Print_ISBN :
978-1-4244-5269-9
Electronic_ISBN :
978-1-4244-5271-2
DOI :
10.1109/VDAT.2010.5496760
