Reliability assessment of voltage controlled oscillators in 32nm high-κ metal gate technology

A general approach to handle end-of-lifetime reliability of voltage controlled LC oscillators in advanced technology nodes is presented. Investigations base upon a state-of-the art LC-VCO design for GSM applications, designed and fabricated in a 32nm high-κ, metal gate technology. We find that mainly non-destructive device degradation in the active bridge leads to small supply current degradation, which significantly increases for elevated supply voltages. Based on the easy accessable parameter `startup supply voltage´, circuit aging is monitored and a simplified model is derived that reveals the contribution of different aging mechanisms. Our approach to map realistic circuit level aging in an accelerated test setup bases on the dominant aging contributor. Comparison of model, simulation and measurement results proves the coherence of this approach and the impact on the performance parameters of the investigated VCO.