Improvement of crystalline quality of 3-inch InP wafers for microelectronics applications

The different steps to decrease the dislocation density in 3-inch Fe doped InP wafers are described. The crystal growth process is a conventional LEC but thermal shields have been added in order to decrease the thermal gradient in the growing crystal. The shape of these shields has been optimized with the help of numerical simulations of heat transfer and thermomechanical stresses. This process has been done step by step with a continuous feedback between calculations and experiments. A 50% reduction of the thermal stresses has been obtained. The effects of these improvements on the dislocation densities have been investigated by EPD and DDX mapping: the dislocation density has dramatically decreased specially in the upper part of the crystal (from 70,000 to 40,000 cm^-2), therefore matching the specifications for microelectronics applications