DocumentCode
2821712
Title
Low power parallel surveillance video encoding system based on joint power-speed scheduling
Author
Jin, Xin ; Goto, Satoshi
Author_Institution
Inf. Technol. Res. Organ., Waseda Univ., Kitakyushu, Japan
fYear
2011
fDate
6-9 Nov. 2011
Firstpage
1
Lastpage
4
Abstract
In this paper, a low power parallel surveillance video encoding system based on joint power-speed scheduling is proposed. The relative relationships among the CPU statuses, total power consumption and encoding speed are analyzed and modeled for multi-core processors. Based on the power directional graph and the relative encoding speed model, the working statuses of the cores are controlled jointly adapting to video encoding workload to minimize the total power consumption. It provides more than 20% power reduction compared with the latest existing system without a penalty on the encoding speed.
Keywords
microprocessor chips; power consumption; scheduling; surveillance; video coding; CPU; low power parallel surveillance video encoding system; multicore processors; power consumption; power directional graph; power-speed scheduling; relative encoding speed model; Encoding; Joints; Multicore processing; Power demand; Scheduling; Surveillance; Testing; DVFS; H.264/AVC; Joint power-speed scheduling; multicore platform; parallel encoding; video encoding;
fLanguage
English
Publisher
ieee
Conference_Titel
Visual Communications and Image Processing (VCIP), 2011 IEEE
Conference_Location
Tainan
Print_ISBN
978-1-4577-1321-7
Electronic_ISBN
978-1-4577-1320-0
Type
conf
DOI
10.1109/VCIP.2011.6115950
Filename
6115950
Link To Document