The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic

Ultra-low-voltage operation efficiently reduces energy consumption of digital circuits. However, subthreshold MOSFET behavior completely modifies the impact of process, voltage and temperature variations. This paper demonstrates that negative Celsius temperatures are highly detrimental to ultra-low-voltage logic, even more than process variations. We experimentally confirm in 65nm CMOS that -40°C operation dramatically increases the delay by 5.3× at 0.4V. Moreover, we report for the first time that negative temperature almost doubles delay sensitivity against voltage and process variations at ultra-low voltage. This worsens cycle time margins and induces dangerous timing uncertainties. Negative temperature is thus a major concern for ultra-low-voltage circuits.