DocumentCode :
2821963
Title :
FPGA design for image processing using a GUI of a web-based VHDL Code Generator
Author :
Schumann, Thomas ; Susanti, Anita Ratna Dewi
Author_Institution :
Fac. of Electr. Eng. & Inf. Technol., Hochschule Darmstadt-Univ. of Appl. Sci., Darmstadt, Germany
fYear :
2011
fDate :
6-9 Nov. 2011
Firstpage :
1
Lastpage :
1
Abstract :
The aim of our web-based VHDL Code Generator, named DiaHDL, is, to translate a component diagram to synthesizable VHDL code [1][2]. In this live demonstration we present the special Graphical User Interface (GUI) of this web- based tool that allows the user to select digital components, customize their parameters und generate the VHDL code. This is done for an FPGA design for image processing, a JPEG encoder. We show the complete design flow from component entry to bit stream generation for programming a Xilinx FPGA device, using the proposed GUI of DiaHDL tool together with Xilinx ISE tool, a standard HDL synthesis tool.
Keywords :
Internet; field programmable gate arrays; graphical user interfaces; hardware description languages; hardware-software codesign; image coding; logic design; program compilers; DiaHDL tool; FPGA design; GUI; JPEG encoder; Web based VHDL code generator; Xilinx FPGA device programming; Xilinx ISE tool; bit stream generation; component diagram; component entry; digital components; graphical user interface; image processing; standard HDL synthesis tool; Electrical engineering; Field programmable gate arrays; Generators; Graphical user interfaces; Hardware; Hardware design languages; Image processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Visual Communications and Image Processing (VCIP), 2011 IEEE
Conference_Location :
Tainan
Print_ISBN :
978-1-4577-1321-7
Electronic_ISBN :
978-1-4577-1320-0
Type :
conf
DOI :
10.1109/VCIP.2011.6115963
Filename :
6115963
Link To Document :
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