A 757Mb/s 1.5 mm2 90nm CMOS soft-input soft-output MIMO detector for IEEE 802.11n

Multiple-input multiple-output (MIMO) wireless technology is the key to meet the demands for data rate, quality-of-service, and bandwidth-efficiency of modern wireless communication systems. MIMO technology is therefore adopted in many recent communication standards, such as IEEE 802.11n. Here, the MIMO detector has a strong impact on the overall system performance. In fact, the full potential of MIMO communication systems can only be achieved by means of iterative MIMO decoding using soft-input soft-output (SISO) data detection. In this paper, we present-to the best of our knowledge-the first VLSI implementation of a SISO detector for iterative MIMO decoding. The presented ASIC supports SISO detection for four spatial streams and enables more than 6 dB signal-to-noise-ratio improvement over state-of-the-art MIMO detectors. The 1.5 mm² ASIC is fabricated in 90nm CMOS and achieves 757 Mb/s, which exceeds the 600 Mb/s IEEE 802.11n peak data-rate.