Title :
A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode
Author :
Tavernier, Filip ; Steyaert, Michiel
Author_Institution :
K.U. Leuven ESAT-MICAS, Heverlee, Belgium
Abstract :
The design and measurement of a high-speed optical receiver is presented. The intrisically low speed of a silicon photodiode is increased by a new photodiode structure which combines a high speed and a high responsivity. On top of this, an equalizer is used to increase the attainable bit rate even more. The receiver, existing from a photodiode, TIA, equalizer and post amplifier is integrated in a standard 130 nm CMOS technology. At a bit rate of 5.5 Gbit/s and an optical input power of -3.4 dBm, the BER is below 10-12. The power consumption is only 58.5 mW.
Keywords :
CMOS integrated circuits; amplifiers; equalisers; error statistics; monolithic integrated circuits; nanoelectronics; optical receivers; photodiodes; power consumption; BER; CMOS; TIA; amplifier; bit rate 5.5 Gbit/s; equalizer; high-speed optical receiver design; high-speed optical receiver measurement; power 58.5 mW; power consumption; silicon photodiode; speed-enhanced integrated photodiode; Bandwidth; Bit rate; Equalizers; High speed optical techniques; Optical receivers; Photodiodes; Substrates;
Conference_Titel :
ESSCIRC, 2010 Proceedings of the
Conference_Location :
Seville
Print_ISBN :
978-1-4244-6662-7
DOI :
10.1109/ESSCIRC.2010.5619763
