A CMOS adaptive equalizer using low-voltage zero generators technique

Author

Tsai, Yu-Chang ; Cheng, Kuo-Hsing ; Wu, Yen-Hsueh ; Lin, Ying-Fu

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

546

Lastpage

549

Abstract

This paper presents a 5 Gb/s adaptive equalizer that compensates for the FR-4 channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency tunable gain boosting without inductors. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the output buffers) at a 1.6 V supply voltage with an output swing of 560 mV (p-p). The area occupied is 0.1 mm² (including output buffers), and output peak-to-peak jitter is 0.28 UI. The equalizer achieves high frequency compensation, small area, and low power consumption.

Keywords

CMOS analogue integrated circuits; adaptive equalisers; amplifiers; low-power electronics; CMOS adaptive equalizer; bit rate 5 Gbit/s; current steering; frequency 2.5 GHz; loss 14 dB; low-voltage zero generators technique; power 17.6 mW; pre-amplifier circuit; voltage 1.6 V; voltage 560 mV; Adaptive equalizers; Boosting; Detectors; Gain; Impedance; Simulation; Adaptive equalizer; equalizing filter; high-speed serial links; inductorless; power detector;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2010 Proceedings of the

Conference_Location

Seville

ISSN

1930-8833

Print_ISBN

978-1-4244-6662-7

Type

conf

DOI

10.1109/ESSCIRC.2010.5619764

Filename

5619764