Knowledge based systems used in design for testability-an an overview

In choosing a design for testability technique for a given VLSI circuit the designer must match the attributes of the technique, that is, area overhead, pin out, fault coverage, etc., against the constraints of the design specification. In the selection process, a large number of trade-offs must be considered and since there is no unified theory about the integration of design for testability structures into a circuit a vast solution space must be explored for the optimal scheme. The characteristics of this type of problem, however, are well suited to a solution using expert system techniques. A brief description of some of the systems used to integrate DFT structures in a circuit is given