HIT: hierarchical integrated test methodology

In HIT a hierarchical integrated test methodology, the authors use a knowledge base to store the properties of previously characterised circuit elements called cells. Cells are divided into four categories: combinational (e.g. PLA random logic), memory (e.g. RAM, CAM), Register (e.g. latches, flip-flops, a combinational block containing a register) and Bus structures (fan-outs, bus concatenation, sign extend, bus select). Each cell has various attributes attached such as test vectors or test strategy, transparency, sequentiality and other parameters to reflect the ease of expressing its functionality. A structure comprising of a collection of these cells is termed a design. Once a design has been fully characterised (test process and functionality established) it can be used as a cell in a future design thus reflecting the hierarchy in HIT. HIT has the following potential advantages: significant reduction in test effort and efficiency, reduction in computation since propagation is along busses of arbitrary width, test patterns can be generated at an arbitrary level, it creates a dialogue between the designer and testability expert which in most cases will result in an improved design