Title :
Concurrent automatic test pattern generation
Author :
Taylor, G.E. ; Bannister, B.R. ; Miller, P.J.
Author_Institution :
Dept. of Electr. Eng., Hull Univ., UK
Abstract :
Of the four main techniques for the automatic generation of test patterns for digital circuits the authors discuss algebraic techniques. The most widely known algebraic technique is that of Boolean Difference in which boolean functions G(X), F(X) describing the fault free and faulty circuits respectively are produced. A test function T(X) is formed from the exclusive-OR of G(X) and F(X). As an alternative to forming the complete test set and post processing to determine an appropriate test sequence, patterns which test for particular faults may be selected directly from the table. If, for example, a go/no-go test set is required a useful heuristic is to first find a pattern which detects a fault among those with lowest testability. Using either the fault augmented function (via evaluation of a small subset of its truth table) or fault simulation techniques other faults detected by the chosen pattern can be determined and eliminated from the table describing A(X,F). This process is then repeated for one of the remaining faults until a full fault cover has been obtained
Keywords :
logic CAD; logic testing; Boolean Difference; IC testing; XOR operation; algebraic techniques; automatic test pattern generation; concurrent error detection; digital circuit testing; exclusive-OR; fault augmented function; fault simulation techniques; full fault cover; go/no-go test set; test for particular faults;
Conference_Titel :
Algorithmic and Knowledge Based CAD for VLSI, IEE Colloquium on
Conference_Location :
London