Guaranteeing optimality in a gridless router using AI techniques

Addresses the problem of automating the generation of interblock routing within the chip assembly phase of full-custom integrated circuit design. An algorithm is presented which performs routing in the gridless domain and generates the mask-layout directly from a set of user-specified design rules. The algorithm guarantees (i) to find a route if one exists and (ii) that there is no route of a lesser cost than the one found. This is achieved by adopting a technique used in Artificial Intelligence to control a search of an edge-list database. The time complexity of the algorithm is low, and is independent of the resolution of the fabrication process. The routing tool carries out individual point-to-point interconnection tasks using a particular optimisation criterion such as minimal track length or minimum via count. The system reads pin positions in absolute dimensions and the process design rules which can include any number of layers. A mask-level routing pattern is produced which can be implemented with a minimum of post-processing