Synthesis by simulated annealing

Author

Neil, J.P. ; Denyer, P.B.

Author_Institution

Dept. of Electr. Eng., Edinburgh Univ., UK

fYear

1989

fDate

32818

Firstpage

42614

Lastpage

42617

Abstract

Summarises work proceeding towards the development of a suite of algorithmic optimisation tools intended to operate in a directed silicon compilation environment. The tools are controlled by the stochastic computational technique known as simulated annealing. The paper contains a description of the scheduling and allocation problem, together with a description of the simulated annealing algorithm. There then follows a brief discussion of results obtained thus far together with some indications of future work

Keywords

VLSI; circuit layout CAD; algorithmic optimisation tools; scheduling and allocation problem; silicon compilation environment; simulated annealing algorithm; stochastic computational technique;

fLanguage

English

Publisher

iet

Conference_Titel

Algorithmic and Knowledge Based CAD for VLSI, IEE Colloquium on

Conference_Location

London

Type

conf

Filename

198931

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=282269